Method, System, Medium, and Electronic Device for Optimizing Fault-Tolerant Neural Network Structure
Published in China National Intellectual Property Administration
A method for optimizing fault-tolerant neural network architectures using Bayesian optimization, addressing resistance variation and bit-flip in ReRAM devices.
Recommended citation: N. Ye, Z. Fang, J. Mei. "Method, System, Medium, and Electronic Device for Optimizing Fault-Tolerant Neural Network Structure." CN Patent CN113,570,056 A, 2021.